Direct memory access (DMA) is a method typically used to transfer large amounts of data between a host central processing unit (CPU) and a DMA input/output (I/O) device. Briefly, the host CPU provides the DMA I/O device with information about where to place (for input) or from where to fetch (for output) data from the host memory such that the I/O device can independently perform the data transfer operation. As a result of the I/O device independently performing the I/O operation, the host CPU is relieved of handling much of the processing associated with the I/O operation.
The information about where to place or from where to fetch, among other information describing and/or controlling the to-be-performed data transfer, is known as independently performing the I/O operation, the host CPU is relieved of handling much of the processing associated with the I/O operation.
The information about where to place or from where to fetch, among other information describing and/or controlling the to-be-performed data transfer, is known as “overhead information”, and the overhead information is transferred from the host CPU to the I/O device as part of the data transfer. For example, the volume of data to be transferred may be so large that it does not fit contiguously into the host memory. In this case, different regions of the host memory may be utilized and the locations of these different regions are conveyed to the I/O device in the transfer of overhead information from the host CPU. The host CPU typically is informed of the arrival DMA data through status information on a pre-determined status page in host memory.
The information exchanged in the DMA transfer between the host CPU and I/O device includes network packets, status information or free-list information. The network packets are transferred from the host using host network send packet buffers, and are transferred to the host using network receive packet buffers. The network receive packet buffers include a global anonymous pool of buffers referred to as free-list buffers, and also tagged pool buffers. Finally, status information from the I/O device to the CPU device is usually implemented using a pre-determined location in CPU memory. The I/O device writes to this status location to inform the CPU about progress in carrying out the CPU requested DMA operations, and informs the CPU about packets that the I/O device has written to the CPU memory.